The disclosed embodiments of the present invention relate to accessing buffered data (e.g., cached data), and more particularly, to a storage system having multiple tag entries associated with the same data storage line (e.g., the same cache line) for data recycling and related tag storage device.
In today's systems, the time it takes to bring data (e.g., instructions) into a processor is very long when compared to the time to process the data. Therefore, a bottleneck forms at the input to the processor. The cache memory helps by decreasing the time it takes to move information to and from the processor. When the cache memory contains the information requested, the transaction is said to be a cache hit. When the cache memory does not contain the information requested, the transaction is said to be a cache miss. In general, the hit rate is a critical performance index of the cache memory. How to increase the hit rate has become an issue in the field.
The cache memory may be a fully associative cache, a direct-mapped cache, or a set-associative cache. The set-associative cache is a hybrid between the fully associative cache and the direct-mapped cache, and may be considered a reasonable compromise between the hardware complexity/latency of the fully associative cache and the direct-mapped cache. To increase the hit rate of the set-associative cache, the conventional design may try to increase ways of a set. But there is a limited benefit to increase ways of a set. For example, when the number of ways of a set is changed from 8 to 16, the hit rate will not increase too much, but the gate count and complexity will increase. Besides increasing the ways of a set, the conventional design may modify the replacement rule employed. But it also hit to the limitation for increasing the hit rate.